This invention relates to a CDMA receiver and, more particularly, to a CDMA receiver for receiving a signal containing data that has been spread by a predetermined spreading code sequence, calculating a correlation value between a reference code sequence and a spread data sequence obtained by sampling the received signal at a predetermined sampling rate, and adopting, as despread start timing, the timing at which the correlation value is maximized.
Competition to develop ever smaller terminals in the field of modern mobile communications is intense and there is a need to reduce the power consumed by these terminals.
Digital cellular wireless communication systems using DS-CDMA (Direct-Sequence Code Division Multiple-Access) technology have been developed as next-generation mobile communication systems for implementing wireless multimedia communication. In a CDMA digital cellular wireless communications system of this kind, a base station transmits control information and user information upon multiplexing the information with a spreading code. Individual mobile stations receive the control information from the base station, spread the transmission information using a spreading code specified by the base station and then send the information. By accepting this control information, each mobile station is capable of performing a variety of control operations. For example, the mobile station performs position registration and acquisition of information concerning base stations in the area and carries out control for call origination and incomingcall standby. In order for a mobile station to receive control information from the base station in a CDMA digital cellular wireless communications system of this kind, it is necessary to identify the start timing (phase) of spread data that has undergone spread-spectrum modulation.
FIG. 13 is a diagram showing the construction of a CDMA transmitter in a base station device which sends transmission data of control and user channels upon code-multiplexing the data. The transmitter includes spread-spectrum modulators 111-11n of respective control/user channels, each having a frame generator 21, a serial/parallel (S/P) converter 22 for converting frame data to parallel data, and a spreading circuit 23. The frame generator 21 includes a transmission data generator 21a for generating serial transmission data D1, a pilot signal generator 21b for generating a pilot signal P, and a framing circuit 21c for forming the serial data D1 into blocks a prescribed number of bits at a time and inserting the pilot signal P before and after every block to thereby form frames. The pilot signal, when all xe2x80x9c1xe2x80x9ds, for example, allows the receiver to recognize the amount of phase rotation caused by transmission so that the data may be subjected to a phase rotation of an equivalent amount in the opposite direction.
The S/P converter 22 alternately distributes the frame data (the pilot signals and transmission data) one bit at a time to convert the frame data to I-component (in-phase component) data DI and Q-component (quadrature-component) data DQ.
The spreading circuit 23 includes a pn sequence generator 23a for generating a pn sequence (long code) specific to the base station, an orthogonal Gold code generator 23b for generating an orthogonal Gold code (short code) specific to the control channel and user channel, an EX-OR gate 23c for outputting a spreading code C1 by taking the exclusive-OR between the long code and the short code, and EX-OR gates 23d, 23e for performing spread-spectrum modulation by taking the exclusive-ORs between the data DI and DQ (symbols) respectively, and the spreading code C1. It should be noted that since xe2x80x9c1xe2x80x9d is level xe2x88x921 and xe2x80x9c0xe2x80x9d is level +1, the exclusive-OR between signals is the same as the product between them.
Also shown in FIG. 13 are a combiner 12i for outputting an I-component code-multiplexed signal xcexa3VI by combining the I-component spread-spectrum modulated signals VI output by the respective spread-spectrum modulators 111xcx9c11n of the user channel; a combiner 12q for outputting a Q-component code-multiplexed signal xcexa3VQ by combining the Q-component spread-spectrum modulated signals VQ output by the respective spread-spectrum modulators 111xcx9c11n; FIR-type chip shaping filters 13i, 13q for limiting the bandwidths of the code-multiplexed signals xcexa3VI, xcexa3VQ, respectively; DA converters 14i, 14q for converting the analog outputs of the respective filters 13i, 13q to analog signals; a quadrature modulator 15 for applying quadrature phase-shift keying (QPSK) modulation to the code-multiplexed signals xcexa3VI, xcexa3VQ of the I and Q components and outputting the modulated signal; a transmitting circuit 16 for converting the output signal frequency of the quadrature modulator to a radio frequency, applying high-frequency amplification and then outputting the signal, and an antenna 17.
FIG. 14 is a diagram illustrating the construction of the receiver of a mobile station. The receiver includes an antenna 21; a receiver circuit 22 for performing amplification and frequency conversion from RF (radio frequency) to IF (intermediate frequency); a QPSK detector 23 for performing QPSK detection and outputting I, Q signals; an AD converter 24 for converting baseband analog I, Q signals, which are the detector outputs, to digital I, Q data, respectively; a despreading circuit 25 for performing despreading by multiplying the I, Q data by a spreading code sequence identical with that of the base station; a data demodulator 26 for performing synchronous detection, data discrimination and error correction; and a searcher 27.
The searcher 27 has a matched filter 31 for performing correlation, a timing identification unit 32 for identifying spread start timing (phase), and a code table 33 for generating a reference code sequence. The matched filter 31 performs a correlation operation between a received spread data sequence and the reference code sequence in order to identify the despread start timing. The timing identification unit 32 acquires the spread start timing (phase) based upon the timing at which a correlation value between the received spread data sequence and the reference code sequence exceeds a set level.
FIG. 15 is a diagram useful in describing the structure of the matched filter and a method of specifying despread timing. The matched filter 31 includes an (n+1)-chip shift register (s0-Sn) 31a for successively shifting a spread data sequence of the baseband at the chip frequency fc; an (n+1)-chip shift register (c0-cn) 31b for storing the spreading code sequence, which is the reference code sequence, at the chip frequency; (n+1)-number of multipliers (MP0-MPn) 31c for multiplying corresponding bits of the baseband spread data sequence and reference code sequence; and an adder circuit 31d for adding the outputs of the multipliers.
When the correlation between the received spread data sequence and reference code sequence is calculated by the matched filter (MF) 31, the correlation value becomes large at the moment the spread data sequence and reference code sequence coincide. Accordingly, the timing identification unit 32 monitors the correlation value output by the matched filter 31, identifies the moment the correlation value exceeds the set level as being the despread start timing and outputs a signal indicative of this.
The foregoing relates to a case where the input to the shift register 31a is a spread data sequence obtained by sampling the output signal of the quadrature detector 23 (FIG. 14) at the chip frequency fc and converting this analog signal to digital data. A single correlation value is obtained per chip. However, if the sampling frequency is made high, a plurality of correlation values can be obtained per chip. FIG. 16 is a diagram for describing the results of simulation indicating the relationship between number of oversamplings and correlation-value output. FIG. 16 shows the correlation-value output of the matched filter at the time of eight oversamplings whose sampling frequency is equal to 8xc3x97fc. The simulation conditions are as follows:
(1) spreading code: M sequence (x18+x7+1)
(2) spreading rate: 16
(3) number of matched-filter taps: 256
(4) roll-off characteristic: substituted by sine curve
It is evident from this correlation-value output characteristic of the matched filter that eight correlation values can be obtained per chip by eight oversamplings. For example, assume that the correlation-value output when the location on the eye pattern having the largest opening is sampled is 1. The output declines by about 0.5 dB when the offset is 1/8 chip and by about 3 dB when the offset is 2/8 chip. There is no correlation value output when the offset is 4/8 chip.
(1) If the sampling frequency is made n times the chip frequency, i.e., if there are n oversamplings, correlation values can be obtained at phase intervals of 1/n chip. Accordingly, in comparison with a case in which the sampling frequency is equal to the chip frequency, the timing at which the correlation value is maximized, namely the despread timing, can be obtained at a phase precision that is n times greater.
(2) It will be understood from the correlation-value output characteristic of the matched filter that a correlation output is not obtained unless the timing of the correlation calculation of the matched filter is shifted from the normal timing by xc2x11/2 chip or more, and that the correlation output becomes small if the phase difference takes on a large value, even if the shift (phase difference) is less than 1/2 chip.
FIG. 17 is graph showing the relationship between the receiving line quality (C/N ratio) and BER (Bit Error Rate) in a case where the number n of oversamplings is 4, 8, 16. Numeral 1 in FIG. 17 denotes a BERxe2x88x92C/N ratio characteristic at the time of four oversamplings (n=4), 2 a BERxe2x88x92C/N ratio characteristic at the time of eight oversamplings, and 3 a BERxe2x88x92C/N ratio characteristic at the time of 16 oversamplings. The larger the number of oversamplings, the smaller the BER for the same C/N ratio. Accordingly, it will be understood that even in a case where the state of reception is poor, the BER can be made small if the number of oversamplings is increased.
In a case where despreading is performed, a despread output will not be obtained if the despread timing is shifted by one chip. The larger the phase shift, the smaller the despread output. In particular, if the reception level is low, the influence of the phase shift is large and the bit error increases owing to the phase difference. In the prior art, therefore, the sampling rate of the matched filter is raised to improve the precision with which the despread start timing is detected.
However, as shown in FIG. 15, the matched filter comprises the two shift registers 31a, 31b for the baseband spread data and reference code sequence, respectively, the multiplier circuit 31c for multiplying the baseband spread data and reference code sequence, and the adder circuit 31d for adding the outputs of the multipliers. Furthermore, the A/D converter 24 (FIG. 14) is connected to the matched filter 31. When these components are included, the circuitry becomes extremely large in scale, and the higher the operating frequency, the greater the power consumed. Thus, achieving a low power consumption is difficult. As a consequence, the conventional CDMA receiver, in which the sampling rate of the matched filter is made high, consumes a large amount of power. This is problem that needs to be solved.
Accordingly, an object of the present invention is to provide a CDMA receiver in which power consumption can be reduced and which is capable of maintaining the precision with which despread timing is detected.
In accordance with the present invention, the foregoing object is attained by providing a CDMA receiver comprising a reception-state detector for detecting state of reception, a sampling controller for deciding sampling rate in conformity with the state of reception, a correlator (matched filter) for calculating a correlation between a reference code sequence and a spread data sequence, which is obtained by sampling a received signal at the above-mentioned sampling rate, and a timing detector for obtaining a timing at which the correlation value is maximized and adopting this timing as despread start timing. More specifically, if the state of reception is good, the number of oversamplings is reduced and the operating speed of the matched filter is lowered, thereby making it possible to reduce power consumption. If the state of reception is poor, the number of oversamplings is enlarged to improve the precision with which despread timing is detected.
Examples of detectors that can be used as the reception-state detector for detecting the state of reception are (1) a field-strength detector for detecting the electric field strength of a received signal, (2) an AGC control-voltage detector for detecting the control voltage of an AGC circuit, (3) a power detector for detecting signal power after despreading is performed, (4) a SIR detector for detecting the SIR (Signal Interference ratio) after despreading is performed and (5) a bit error-rate detector for detecting the bit error rate of a received code.
At the initial stage of control, sampling rate is controlled in dependence upon the reception field strength or AGC control voltage and then sampling rate is controlled in dependence upon despread-signal power or SIR, or sampling rate is controlled further in dependence upon bit error rate. If this arrangement is adopted, the sampling rate of a matched filter can be controlled from an early stage at which channel estimation has not yet been made, such as at the time of initial synchronization, the time needed for the sampling rate to converge to the optimum rate can be shortened and power consumption of the CDMA receiver can be reduced.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings.